Sega 8-bit resources: Difference between revisions
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=== PSG status port === |
==== PSG status port ==== |
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The port at 0xF3 allows the program to know the state of each PSG, which means that it reduces the complexity of programming them by the former restriction of writing cycle-accurate code. |
The port at 0xF3 allows the program to know the state of each PSG, which means that it reduces the complexity of programming them by the former restriction of writing cycle-accurate code. |
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As the highmost bits are invalid, the value obtained from reading this port must be masked. |
As the highmost bits are invalid, the value obtained from reading this port must be masked. |
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=== Test programs === |
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! Program !! Element to test !! Description |
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| [[Media:Sega Master System - Audio control port test.sms|ACR Test]] || Port 0xF2 || Looped series of reads and writes to the audio control port |
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| [[Media:Sega Master System - PSG 0 (write).sms|PSG 0 (write)]] || Port 0x7F || Looped series of writes to PSG 0 |
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| [[Media:Sega Master System - PSG 1 (write).sms|PSG 1 (write)]] || Port 0x7E || Looped series of writes to PSG 1 |
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| [[Media:PSG 2 write.sms|PSG 2 (write)]] || Port 0x7D || Looped series of writes to PSG 2 |
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| [[Media:PSG 3 write.sms|PSG 3 (write)]] || Port 0x7C || Looped series of writes to PSG 3 |
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Latest revision as of 15:22, 7 December 2024
Quad 76489 PSG Synthesizer
A heavily modified ALF MC-1 synthesizer ported from the Apple II to the Sega Master System. It has many differences from the original one as well as traits derivated from its Master system interface.
Features
- Has four PSGs instead of the three the vast majority of MC-1 cards wore
- Four bit latches have been replaced by eight bit ones
- There is a latch per integrated circuit instead of one per board
- Due to the different system frequencies, the synthesizers of this construction work at a different frequency than the original design
- Two of the synthesizers have their frequency divided by two and four, respectively
- The design implements the audio control port with as a three bit register
- The enable logic allows to have PSGs and FM modes
- A new register has been added in order to poll the state of each synthesizer
I/O Port description
| Port | Read | Write | Description |
|---|---|---|---|
| 0x7C | No | Yes | 76489 PSG 0 control port |
| 0x7D | No | Yes | 76489 PSG 1 control port |
| 0x7E | No | Yes | 76489 PSG 2 control port |
| 0x7F | No | Yes | 76489 PSG 3 control port |
| 0xF2 | Yes | Yes | Audio control port |
| 0xF3 | Yes | No | PSG status port |
PSG control ports
The commands to control each PSG don't differ from the ones to control the internal one. However, as the chosen ports collide with the built-in one and as there is no mechanism to disable the integrated PSG, its function must be mutually exclusive.
Audio control port
Another bit is being used by the implementation of the port at 0xF2, in a way that allows to enable or disable the external PSG synthesizer.
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|
| Invalid | Invalid | Invalid | Invalid | 0 | Synth Enable | PSG Enable | FM Enable |
The highmost bits cannot be used in read mode, and although there is no effect otherwise in write mode they should be zero.
| Bit 2 | Bit 1 | Bit 0 | Description |
|---|---|---|---|
| 0 | 0 | 0 | Internal PSG only |
| 0 | 0 | 1 | FM only |
| 0 | 1 | 0 | No sound |
| 0 | 1 | 1 | Internal PSG and FM |
| 1 | 0 | 0 | Synthesizer |
| 1 | 0 | 1 | Synthesizer and FM |
| 1 | 1 | 0 | Reserved |
| 1 | 1 | 1 | Reserved |
PSG status port
The port at 0xF3 allows the program to know the state of each PSG, which means that it reduces the complexity of programming them by the former restriction of writing cycle-accurate code.
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|
| Invalid | Invalid | Invalid | Invalid | PSG 3 ready | PSG 2 ready | PSG 1 ready | PSG 0 ready |
As the highmost bits are invalid, the value obtained from reading this port must be masked.
Test programs
| Program | Element to test | Description |
|---|---|---|
| ACR Test | Port 0xF2 | Looped series of reads and writes to the audio control port |
| PSG 0 (write) | Port 0x7F | Looped series of writes to PSG 0 |
| PSG 1 (write) | Port 0x7E | Looped series of writes to PSG 1 |
| PSG 2 (write) | Port 0x7D | Looped series of writes to PSG 2 |
| PSG 3 (write) | Port 0x7C | Looped series of writes to PSG 3 |