Bits Passats

IBM System/23 Datamaster: Difference between revisions

← Older editNewer edit →
Content deleted Content added
VisualWikitext
No edit summary
Added explanation about probe not displaying results, added explanation that stock 8275s fail test 05h.
(46 intermediate revisions by the same user not shown)
Line 1:
The IBM System/23 Datamaster is the first IBM computer to be based upon an Intel CPU and the only known IBM computer to feature an 8-bit microprocessor. Along with the [[Displaywriter]], is one of the few EBCDIC computersmicrocomputers ever maademade. Development of the hardware began in 1978 and was ready to roll out by late 1979, but due to the late decision to make its BASIC compatible with the one from the System/34 the software delayed its release to July 1981, just one month before the [[IBM 5150 Personal Computer]]. As a result, it was a commercial failure and sold very poorly. While IBM engineers decided to use industry standard components instead of their own SLT family, all references were ofuscated by remarking them with its IBM internal catalog number; this fact difficults enormously their repair and most units are in a state of decay.
 
{| style="float:right;margin:10px;border:1px solid black"
Line 10:
| Models || 5322, 5324
|-
| CPU || Intel 8085@6.14MHz
(effective 3.07MHz)
|-
| DMA || Intel 8257
Line 16 ⟶ 17:
| CRTC || Intel 8275
|-
| Display || 80x2580x24 characters, MDA-like
|-
| ||
|-
| ||
|-
| FDC || NEC 765
Line 26 ⟶ 23:
| RAM || 32KB/64KB/96KB/128KB
|-
| ROM || 112KB/128KB-272KB
|}
 
Line 44 ⟶ 41:
== Hardware Description ==
 
=== Microprocessor and timing ===
The CPU selected to serve as the core of the system was the Intel 8085. However, as the component references were ofuscated identifying the CPU was not a straightforward task. It was hinted that the component with reference 4178015 could be the part. To confirm the true identity of the integrated circuit, an exchange with a legit 8085 was done: the remarked part went into a [[Alphatronic P2|P2]] CPU board and the P2 CPU went in place of the unknown component. The test went successfully and the cross reference was proved as fact.<ref name=":0">Own research</ref>
 
[[File:IBM 8085 CPU being tested in the Alphatronic P2.jpg|thumb|left|alt=IBM 8085 CPU being tested in the Alphatronic P2|IBM 8085 CPU being tested in the Alphatronic P2]]
 
The computer has no specific reset circuit like other computers but it is just triggered by the "Power_Good" signal from the power supply unit.
For more specific information about the 8085 microprocessor, [[8085|refer to its article page]].
 
Regarding the system clock, it is derivated from a 18.432MHz square wave oscillator which is then divided by three to feed the microprocessor with a 6.14MHz signal.
 
It has been found by continuity tests that the SID signal from the CPU is tied to the 5V supply rail. The microprocessor checks its value during test 1 at power-up.
 
=== ROM Operating System ===
Line 88 ⟶ 89:
|}
[[File:ROS Memories.jpg|thumb|left|alt=Some of the sixteen ROS memories|Some of the sixteen ROS memories]]
The ROM Operating System or simply ROS is the firmware of the System/23. It consists in a set of fourteen to sixteen ROMs of 8KB each, for a total of 112KB/128KB, although the service manual states 112KB which means they did not countupdate the non-pagedcapacity after adding ROMs 10h ROMand memory11h<ref>SY34-0171-0 IBM 5322 Computer Service Manual, page 74</ref>. Each ROS ROM has a unique diagnostics identification code, which is determined by the outputs of two 74LS138 3:8 decoders. ROMs 02h and 09h are fixed in the memory map, where the rest are paged in the memory range 4000h-7FFFh. ROMs 0Eh and 0Fh are not present but the logic to select them is implemented even if there is no place to place them in the board; still, with an appropriate ROM adapter their space could be enabled to inject code into the system.
 
ROMs paged 0-7 are present in the board while ROMs paged 8-15 are expected to be provided by expansion cards on their corresponding slots. Therefore, the maximum theoretical ROM capacity for the Datamaster consists of 272KB if the 0Eh-0Fh gap and pages 8-15 are used.
Line 123 ⟶ 124:
 
A common cause of failure for this board and subsequently the whole computer is by having faulty capacitors in shortcircuit in the RAM power supply lines<ref name=":0" />. By simply removing them the issue is solved. In case of 4132 failure, each 4132 upper and lower packages must be separated in order to run the tests.
 
=== Video Subsystem ===
The video subsystem is almost copied verbatim from the Intel 8275 Datasheet. It consists in a 8275 variant plus a 8257 DMA device. The 4178629 made by Intel is the CRTC chip and it behaves slightly different from stock 8275s when activating the interrupts. This small difference makes the test 05 fail with standard 8275s without a patch on ROS 02h. Otherwise, the Datamaster's CRTC has the same pinout and accepts the same commands and parameters than the regular components.
 
=== Diagnostics port ===
Line 133 ⟶ 137:
 
=== Keyboard ===
The computer presents itself with a pre-Model F keyboard with 83 keys. Internally, it used the very same components than the keyboard of the IBM PC would later. The only difference between them is that the PC uses a serial interface to communicate the peripheral with the computer and the Datamaster has a parallel interface. This change also implies that the code in the 8048 micricontrollermicrocontroller both carry is different. For this reason this was also one of the most common causes of not repairable failures.
 
=== Expansion ports ===
The Datamaster has three expansion ports located at the rear of the system. It is important to notice that when the PC was developed most of the pins were left in place and, contrary to the popular belief, one is not the mirrored image of the other.<ref>https://forum.vcfed.org/index.php?threads/system-23-datamaster-i-o-slots.1248011/</ref>
[[File:IBM System 23 expansion port comparison with ISA-8.png|frame|center|alt=IBM Datamaster and PC I/O bus comparison|IBM Datamaster and PC I/O bus comparison]]
 
=== Power Supply Unit ===
Line 146 ⟶ 154:
The IBM System/23 divides its 64KB of addressable space in four segments of 16KB each. All even segments are fixed into the memory map but all the odds are paged and can support up to 16 pages each. The first half portion of the map corresponds to ROM while the last half of it is mapped to RAM<ref>SY34-0171-0 IBM 5322 Computer Service Manual, page 78</ref>.
 
Pagination is achieved thanks to four registers mapped 20h-23h at the I/O space. From those, one determines the ROS page being read, another is used by the DMA mechanism and the other two are used by the CPU access to RAM (for reading and writing, respectively). The widths of each register is four bits, therefore allowing the maximum of sixteen pages. From those, the first eight are expected to be in the board while the remaining are expected to be provided by each expansion card added.
 
Video memory seems to beis placed at address 8000h (to be confirmed)8200h.
 
=== I/O Ports ===
The Datamaster has a rich set of Intel peripherals which consist of a 8251 USART, 8253 PIT, three 8255 PPI, 8257 DMA, 8259 PIC and 8275 CRTC. All of them, including other devices are accessed using the following ports<ref name=":0" />:
{| class="wikitable"
 
! Ports !! Device !! Function
|-
| 00h-0Fh || 8257 || DMA
|-
| 20h || 74LS670 || DMA Page Register
|-
| 21h || 74LS670 || RAM Write Register
|-
| 22h || 74LS670 || RAM Read Register
|-
| 23h || 74LS670 || CPU ROS Page Register
|-
| 24h-27h || 8253 || PIT
|-
| 28h-2Bh || 8259 || PIC
|-
| 2Ch || 8255#1 || Language/Region switches
|-
| 2Dh || 8255#1 || CE/ROM Update switches, RAM configuration
|-
| 2Eh || 8255#1 || Unknown; related to memory test 04
|-
| 2Fh || 8255#1 || 8255#1 control port
|-
| 40h || 8255#2 || Keyboard scan codes
|-
| 41h || 8255#2 || Service port
|-
| 42h || 8255#2 || Keyboard control signals
|-
| 43h || 8255#2 || 8255#2 control port
|-
| 44h-47h || 8275 || CRTC
|-
| 48h-4Bh || 8251 || USART
|-
| 4Ch || 8255#3 || Data bus test register / Character ROM pagination
|-
| 4Dh-4Eh || 8255#3 || C option switches
|-
| 4Fh || 8255#3 || 8255#3 control port
|}
 
=== Interrupts ===
Interrupts in the Datamaster are mostly handled by the 8259 PIC. However, the extra interrupts added by the 8085 are handled directly by the CPU.
{| class="wikitable"
! Interrupt !! Function
|-
| TRAP || 8085 SOD (enable), memory parity error
|-
| RST7.5 || PIT timer 2
|-
| RST6.5 || Unknown
|-
| RST5.5 || 8275 IRQ (if J1 is bridged)
|-
| IRQ || 8259 PIC
|-
| IRQ0 || Keyboard
|-
| IRQ1 || USART
|-
| IRQ2 || USART
|}
 
=== Timers ===
Having a 8253 PIT the computer has access to three independent programmable timers.
{| class="wikitable"
! Timer !! Function
|-
| Timer 0 || Baud rate generator for 8251 USART
|-
| Timer 1 || Beeper
|-
| Timer 2 || 8085 interrupt RST7.5
|}
 
=== Diagnostics ===
The System/23 Datamaster implements a set of self-test routines identified as "PID-1200". With them it tests the CPU, the memory and the different peripherals of the computer. Usually the results of the tests are written to the screen at start-up but if an error occurs before the initialization of the screen a probe is needed. Faulty CPU, ROM or 8255 (units 2 and 3) will prevent any diagnostics to be displayed, even with a probe. The tests are identified by an hexadecimal value and can be presented unstyled, underlined or inverted. In the case of being underlined it means that the feature tested wasn't found by the system, whereas if it is inverted it has been detected but was tested and found faulty. If the text is left unstyled, it means the test passed. The test routines and their tested areas are the following<ref>6841631 System/23 Diagnostic User Guide, page 87</ref>:
 
{| class="wikitable"
! Test !! Description !! Notes
|-
| 00/FF (uninitialized) || Data bus test (undocumented) || writes and reads to port 0x4C (8255#3, port A).
| 01 || CPU and data bus ||
|-
| 01 || CPU || 8085 self-test.
|-
| 02 || First unpaged ROS ROM || ROM at 0000h.
|-
| 03 || Reserved || Unused. Tests pass directly from 02 to 04.
|-
| 04 || RAM || Test for the first unpaged 16KB. Lecture of register 0x2e.
| 02 || First unpaged ROS ROM || This is the ROM at 0000h
|-
| 05 || CRTC, DMA || Interrupt test; initialization of 8275, 8257; light pen test. It fails with standard 8275s.
| 03 || Reserved || Unknown
|-
| 0406 || RAMCRTC || TestSync forand thevideo firstdata 64KBtests.
|-
| 07 || CRT Tube || Tube initialization
| 05-07 || CRTC || Initialization and test; any error in this step or earlier requires a probe
|-
| 08 || Page registers || ForROS CPUpaging access, ROM onlyregister
|-
| 09 || Unpaged ROS ROM || TheROM secondat part of the unpaged segment0x2000
|-
| 10-19 || Paged ROS ROMs in the motherboard || ROMs at 0x4000 and 0x6000
|-
| 1A-29 || ROS Extensions || TestROMs for ROMsat in0x4000 expansionand slots0x6000
|-
| 2A-30 || RAM || Test for the lastpaged 64KBRAM memory
|-
| 31 || Paging Register || For CPU access RAM only
Line 207 ⟶ 302:
|}
 
Note that in case a ROM is unselected or unpowered it will mark its test as "missing". ROMs 0E and 0F aren't present on the board and therefore its tests will always result with a "missing" status.<ref name=":0" /> In the case of early boards with 14 ROMs, 10 and 11 are also marked as missing.
 
== Gallery ==
Retrieved from "https://bitspassats.com/index.php/IBM_System/23_Datamaster"