Bits Passats

IBM System/23 Datamaster: Difference between revisions

← Older edit
Content deleted Content added
VisualWikitext
Added explanation about probe not displaying results, added explanation that stock 8275s fail test 05h.
 
(24 intermediate revisions by the same user not shown)
Line 10:
| Models || 5322, 5324
|-
| CPU || Intel 8085@6.14MHz (effective 3.07MHz)
(effective 3.07MHz)
|-
| DMA || Intel 8257
Line 22 ⟶ 23:
| RAM || 32KB/64KB/96KB/128KB
|-
| ROM || 112KB/128KB-272KB
|}
 
Line 48 ⟶ 49:
 
Regarding the system clock, it is derivated from a 18.432MHz square wave oscillator which is then divided by three to feed the microprocessor with a 6.14MHz signal.
 
It has been found by continuity tests that the SID signal from the CPU is tied to the 5V supply rail. The microprocessor checks its value during test 1 at power-up.
 
=== ROM Operating System ===
Line 86 ⟶ 89:
|}
[[File:ROS Memories.jpg|thumb|left|alt=Some of the sixteen ROS memories|Some of the sixteen ROS memories]]
The ROM Operating System or simply ROS is the firmware of the System/23. It consists in a set of fourteen to sixteen ROMs of 8KB each, for a total of 112KB/128KB, although the service manual states 112KB which means they did not countupdate the non-pagedcapacity after adding ROMs 10h ROMand memory11h<ref>SY34-0171-0 IBM 5322 Computer Service Manual, page 74</ref>. Each ROS ROM has a unique diagnostics identification code, which is determined by the outputs of two 74LS138 3:8 decoders. ROMs 02h and 09h are fixed in the memory map, where the rest are paged in the memory range 4000h-7FFFh. ROMs 0Eh and 0Fh are not present but the logic to select them is implemented even if there is no place to place them in the board; still, with an appropriate ROM adapter their space could be enabled to inject code into the system.
 
ROMs paged 0-7 are present in the board while ROMs paged 8-15 are expected to be provided by expansion cards on their corresponding slots. Therefore, the maximum theoretical ROM capacity for the Datamaster consists of 272KB if the 0Eh-0Fh gap and pages 8-15 are used.
Line 121 ⟶ 124:
 
A common cause of failure for this board and subsequently the whole computer is by having faulty capacitors in shortcircuit in the RAM power supply lines<ref name=":0" />. By simply removing them the issue is solved. In case of 4132 failure, each 4132 upper and lower packages must be separated in order to run the tests.
 
=== Video Subsystem ===
The video subsystem is almost copied verbatim from the Intel 8275 Datasheet. It consists in a 8275 variant plus a 8257 DMA device. The 4178629 made by Intel is the CRTC chip and it behaves slightly different from stock 8275s when activating the interrupts. This small difference makes the test 05 fail with standard 8275s without a patch on ROS 02h. Otherwise, the Datamaster's CRTC has the same pinout and accepts the same commands and parameters than the regular components.
 
=== Diagnostics port ===
Line 150 ⟶ 156:
Pagination is achieved thanks to four registers mapped 20h-23h at the I/O space. From those, one determines the ROS page being read, another is used by the DMA mechanism and the other two are used by the CPU access to RAM (for reading and writing, respectively). The widths of each register is four bits, therefore allowing the maximum of sixteen pages. From those, the first eight are expected to be in the board while the remaining are expected to be provided by each expansion card added.
 
Video memory seems to beis placed at address 8000h (to be confirmed)8200h.
 
=== I/O Ports ===
The Datamaster has a rich set of Intel peripherals which consist of a 8251 USART, 8253 PIT, three 8255 PPI, 8257 DMA, 8259 PIC and 8275 CRTC. All of them, including other devices are accessed using the following ports<ref name=":0" />:
{| class="wikitable"
 
! Ports !! Device !! Function
|-
| 00h-0Fh || 8257 || DMA
|-
| 20h-23h || 74LS670 || DMA Page registersRegister
|-
| 21h || 74LS670 || RAM Write Register
| 24h-27h || PIT
|-
| 22h || 74LS670 || RAM Read Register
| 28h-2Bh || PIC▼
|-
| 23h || 74LS670 || CPU ROS Page Register
| 2Ch-2Fh || 8255#3
|-
| 40h24h-43h27h || Service8253 port|| PIT
|-
| 44h28h-47h2Bh || CRTC8259 || PIC
|-
| 2Ch || 8255#1 || Language/Region switches
| 48h-4Bh || USART▼
|-
| 2Dh || 8255#1 || CE/ROM Update switches, RAM configuration
| 4Ch || Data bus test register▼
|-
| 2Eh || 8255#1 || Unknown; related to memory test 04
| 4Dh-4Fh || Keyboard port▼
|-
| 2Fh || 8255#1 || 8255#1 control port
|-
| 40h || 8255#2 || Keyboard scan codes
|-
| 41h || 8255#2 || Service port
|-
| 42h || 8255#2 || Keyboard control signals
|-
| 43h || 8255#2 || 8255#2 control port
|-
| 44h-47h || 8275 || CRTC
|-
▲| 48h-4Bh || 8251 || USART
|-
▲| 4Ch || 8255#3 || Data bus test register / Character ROM pagination
|-
| 4Dh-4Eh || 8255#3 || C option switches
|-
| 4Fh || 8255#3 || 8255#3 control port
|}
 
=== Interrupts ===
Interrupts in the Datamaster are mostly handled by the 8259 PIC. However, the extra interrupts added by the 8085 are handled directly by the CPU.
{| class="wikitable"
! Interrupt !! Function
|-
| TRAP || 8085 SOD (enable), memory parity error
|-
| RST7.5 || PIT timer 2
|-
| 03 || ReservedRST6.5 || Unknown▼
|-
| RST5.5 || 8275 IRQ (if J1 is bridged)
|-
▲| 28h-2BhIRQ || 8259 PIC
|-
▲| 4Dh-4FhIRQ0 || Keyboard port
|-
| IRQ1 || USART
|-
| IRQ2 || USART
|}
 
Line 192 ⟶ 240:
 
=== Diagnostics ===
The System/23 Datamaster implements a set of self-test routines identified as "PID-1200". With them it tests the CPU, the memory and the different peripherals of the computer. Usually the results of the tests are written to the screen at start-up but if an error occurs before the initialization of the screen a probe is needed. Faulty CPU, ROM or 8255 (units 2 and 3) will prevent any diagnostics to be displayed, even with a probe. The tests are identified by an hexadecimal value and can be presented unstyled, underlined or inverted. In the case of being underlined it means that the feature tested wasn't found by the system, whereas if it is inverted it has been detected but was tested and found faulty. If the text is left unstyled, it means the test passed. The test routines and their tested areas are the following<ref>6841631 System/23 Diagnostic User Guide, page 87</ref>:
 
{| class="wikitable"
! Test !! Description !! Notes
|-
| 00/FF (uninitialized) || Data bus test (undocumented) || writes and reads to port 0x4C (8255 managing keyboard#3, port A).
|-
| 01 || CPU || 8085 self-test.▼
|-
| 02 || First unpaged ROS ROM || This is the ROM at 0000h.▼
|-
| 03 || Reserved || Unused. Tests pass directly from 02 to 04.
▲| 01 || CPU || 8085 self-test
|-
| 04 || RAM || Test for the first unpaged 16KB. Lecture of register 0x2e.
▲| 02 || First unpaged ROS ROM || This is the ROM at 0000h
|-
| 05 || CRTC, DMA || Interrupt test; initialization of 8275, 8257; light pen test. It fails with standard 8275s.
▲| 03 || Reserved || Unknown
|-
| 0406 || RAMCRTC || TestSync forand thevideo firstdata 64KBtests.
|-
| 07 || CRT Tube || Tube initialization
| 05-07 || CRTC || Initialization and test; any error in this step or earlier requires a probe
|-
| 08 || Page registers || ForROS CPUpaging access, ROM onlyregister
|-
| 09 || Unpaged ROS ROM || TheROM secondat part of the unpaged segment0x2000
|-
| 10-19 || Paged ROS ROMs in the motherboard || ROMs at 0x4000 and 0x6000
|-
| 1A-29 || ROS Extensions || TestROMs for ROMsat in0x4000 expansionand slots0x6000
|-
| 2A-30 || RAM || Test for the lastpaged 64KBRAM memory
|-
| 31 || Paging Register || For CPU access RAM only
Line 250 ⟶ 302:
|}
 
Note that in case a ROM is unselected or unpowered it will mark its test as "missing". ROMs 0E and 0F aren't present on the board and therefore its tests will always result with a "missing" status.<ref name=":0" /> In the case of early boards with 14 ROMs, 10 and 11 are also marked as missing.
 
== Gallery ==
Retrieved from "https://bitspassats.com/index.php/IBM_System/23_Datamaster"