IBM System/23 Datamaster: Difference between revisions

Pagination is achieved thanks to four registers mapped 20h-23h at the I/O space. From those, one determines the ROS page being read, another is used by the DMA mechanism and the other two are used by the CPU access to RAM (for reading and writing, respectively). The widths of each register is four bits, therefore allowing the maximum of sixteen pages. From those, the first eight are expected to be in the board while the remaining are expected to be provided by each expansion card added.

 

 

=== I/O Ports ===

| 00h-0Fh || 8257 || DMA

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| 24h-27h || 8253 || PIT